Images are a common problem when digital-to-analog converters (DACs) are employed to reproduce analog waveforms. In general, DACs have a zero-order hold output. If samples representing a signal having a frequency, F, are applied to a zero-order hold DAC clocked at a sample frequency, Fs, the output will have spectral images at (F+/−kFs), for every integer k. FIG. 1A illustrates some of the problems associated with spectral images for a DAC of conventional design. Referring to FIG. 1A, digitized samples of a signal having a frequency F=1 MHz are applied to a zero-order hold DAC clocked at a sampling frequency (150) of Fs=8 MHz. The resulting spectral images are illustrated at (8−1) MHz (141) and (8+1) MHz (142), as well as (16−1) MHz (143) and (16+1) MHz (144). The amplitudes of the spectral images have a slow sinc roll-off (not shown). For the example of FIG. 1A, the 1 MHz sinusoidal signal sampled at an 8 MHz sampling frequency (150) has spectral images at 7 MHz (141), 9 MHz (142), 15 MHz (143), 17 MHz (144), and so on. One conventional method of removing the spectral images involves filtering the output of the DAC using a low-pass filter, as shown in FIG. 1B.
FIG. 1B illustrates suppression of the spectral images shown in FIG. 1A, by employing passband filtering of the output of a DAC of conventional design. Referring to FIG. 1B, during passband filtering, the desired 1 MHz signal (110) falls within the passband of a filter having the illustrated response curve (120), while the spectral images (141)–(148) fall within the stopband of the filter. High-quality filters with sharp cutoff frequencies are difficult to build, and are often expensive. A common way to reduce the cost of the filter is to use a higher sample clock frequency, Fs (150), in order to move the spectral images further from the signal of interest.
FIG. 1C is a diagram that illustrates filtering in a DAC of conventional design utilizing a higher clock or sampling frequency, Fs (150). Referring to FIG. 1C, filtering using the higher sample clock frequency (150) permits the use of a filter having a slower cutoff as shown by the response curve (120) illustrated in FIG. 1C. Such a response curve reduces the cost of the filter, when compared to filters having a sharper response. However, DACs that operate at the higher sampling frequency (150) are difficult to design, and are typically more expensive than those operating at lower frequencies. First-order as well as higher-order holds are possible, and are sometimes mentioned in research, but implementation is usually not practical.
Many conventional DACs are built from a number of switched current sources. There are several different arrangements for such switched current sources. A simple 10-bit DAC, for example, may have 10 binary-weighted current sources, or 1024 uniformly-weighted current sources. Switching the current sources on or off changes the output current proportional to the 10-bit digital input. Each digital value at the input is thereby converted into an analog current strength at the output. FIG. 1D is a block diagram of a conventional DAC.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of ordinary skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.